المصدر: VHDL and FPGA في منتدى : قسم البرامج وقواعد البيانات والفيديوهات الهندسية I have the following design should be written in VHDL language program, so can you help me. My design shall accept a 50 megahertz clock signal, an asynchronous active low reset signal, an asynchronous 1-bit load signal, two asynchronous 4-bit data signals. The design shall add the two asynchronous 4-bit data signals at the rising edge of the load signal and display the result in hexadecimal or decimal using the 7-seqment hex display. The 4-bit adder shall be implemented in a procedure and the procedure shall be implemented in a package. The main program shall call the procedure from the package when needed.
