Gate leakage variability in nano-CMOS transistors
لجنة مناقشـــة متساهلة ومضمونة
لجنة مناقشـــة متساهلة ومضمونة
Gate leakage variability in nano-scale CMOS devices is investigated through advanced modelling and simulations of planar, bulk-type MOSFETs. The motivation for the work stems from the two of the most challenging issues in front of the semiconductor industry - excessive leakage power, and device variability - both being brought about with the aggressive downscaling of device dimensions to the nanometer scale. The aim is to deliver a comprehensive tool for the assessment of gate leakage variability in realistic nano-scale CMOS transistors
Link
http://theses.gla.ac.uk/771/01/2009markovphd.pdf
Link
http://theses.gla.ac.uk/771/01/2009markovphd.pdf