Full-Chip Nanometer Routing Techniques
By Tsung-Yi Ho, Yao-Wen Chang, Sao-Jie Chen
Springer | 2007-08-20 | ISBN: 1402061943 | 102 pages | PDF | 7.1 MB
At 90 nm, wires account for nearly 75% of the total delay in a circuit. Even more insidious, however, is that among nearly 40% of these nets, more than 50% of their total net capacitance are attributed to the cross-coupling capacitance between neighboring signals. At this point a new design and optimization paradigm based on real wires is required. Nanometer routers must prevent and correct these effects on-the-fly in order to reach timing closure. From a manufacturability standpoint, nanometer routers must explicitly deal with the ever increasing design complexity, and be capable of adapting to the constraint requirements of timing, signal integrity, process antenna effect, and new interconnect architecture such as X-architecture.
http://ifile.it/zqc532t/2RG6ZfBnH.7z
archive password:ebooksclub.org
By Tsung-Yi Ho, Yao-Wen Chang, Sao-Jie Chen
Springer | 2007-08-20 | ISBN: 1402061943 | 102 pages | PDF | 7.1 MB
At 90 nm, wires account for nearly 75% of the total delay in a circuit. Even more insidious, however, is that among nearly 40% of these nets, more than 50% of their total net capacitance are attributed to the cross-coupling capacitance between neighboring signals. At this point a new design and optimization paradigm based on real wires is required. Nanometer routers must prevent and correct these effects on-the-fly in order to reach timing closure. From a manufacturability standpoint, nanometer routers must explicitly deal with the ever increasing design complexity, and be capable of adapting to the constraint requirements of timing, signal integrity, process antenna effect, and new interconnect architecture such as X-architecture.
http://ifile.it/zqc532t/2RG6ZfBnH.7z
archive password:ebooksclub.org