abdoud
New Member
Microwind 2
The MicroWind2 program allows the student to design and simulate an integrated circuit at physical description level. The package contains a library of common logic and analogue ICs to view and simulate. MicroWind2 includes all the commands for a mask editor as well as original tools never gathered before in a single module (2D and 3D process view, VERILOG compiler, tutorial on MOS devices). The student can gain access to circuit simulation by pressing one single key. The electric extraction of a circuit is automatically performed and the analogue simulator produces voltage and current curves immediately."
The MicroWind2 program allows the student to design and simulate an integrated circuit at physical description level. The package contains a library of common logic and analogue ICs to view and simulate. MicroWind2 includes all the commands for a mask editor as well as original tools never gathered before in a single module (2D and 3D process view, VERILOG compiler, tutorial on MOS devices). The student can gain access to circuit simulation by pressing one single key. The electric extraction of a circuit is automatically performed and the analogue simulator produces voltage and current curves immediately."
You may edit boxes, using a palette of layers. You may cut, paste, duplicate, generate matrix of layout, and use the layout editor to insert contacts, MOS devices, pads, complex contacts and path in one single click.
Chip Layout of BCD Addder.
Layout of 2-bit Analog to Digital Converter.
Verilog Compiler
Features
Sub-micron, deep-submicron, nanoscale technology support.
Unsurpassed illustration capabilities.
Design-error-free cell library (Contacts, vias, MOS devices, etc.).
Advanced macro generator (Capacitor, MOS transistor, matrix, ROM, pads, inductors, path, etc.)
Virtual components library.
Incredible translator from logic expression into compact design-error free layout.
Powerful automatic compiler from VERILOG circuit into layout.
On-line design rule checker: width, spacing, overlap, extension rule verification.
Built-in extractor which generates a SPICE netlist from layout.
Extraction of all MOS width and length.
Parasitic capacitance, crosstalk and resistance extracted for all electrical nodes.
Import/Export CIF layout from 3rd party layout tools.
Up to 100,000 elementary boxes.
Lock & unlock layers to protect some part of the design from any changes.
Enhanced editing commands and layout control.
User Palette
DOWNLOAD
22 MB .
